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When designing combinational circuits. We discussed five steps:
We will look at designing a combinational circuit for a Half-Adder.
0 + 0 = 00 where sum = 0, carry = 0 0 + 1 = 01 where sum = 1, carry = 0 1 + 0 = 01 where sum = 1, carry = 0 1 + 1 = 10 where sum = 0, carry = 1
You should be able to fill in the boxes for c and s:
Input |
Output |
|||
x |
y |
c |
s |
|
0 |
0 |
0 |
0 |
|
0 |
1 |
0  |
1  |
|
1 |
0 |
0 |
1 |
|
1 |
1 |
1  |
0  |
Here is where we cheat a little. We will not use the Karnaugh maps. Because you have a simple truth table (4 rows), you can match the gates with the gates you already know.
Here are the truth tables for the gates you know:
x | y | AND | NAND | NOR | OR | XOR |
0 | 0 | 0 | 1 | 1 | 0 | 0 |
0 | 1 | 0 | 1 | 0 | 1 | 1 |
1 | 0 | 0 | 1 | 0 | 1 | 1 |
1 | 1 | 1 | 0 | 0 | 1 | 0 |
We can get the following expressions by observation. There are two inputs, two gates, and two outputs.
s = x XOR y c = xy
You can now try and use two half-adders to create a full adder. Again, we will break the problem into steps:
0 + 1 + 0 = 01 where carry = 0, sum = 1, 0 + 0 + 1 = 01 where carry = 0, sum = 1, 1 + 0 + 1 = 10 where carry = 1, sum = 0, 1 + 1 + 1 = 11 where carry = 1, sum = 1,
Fill in the truth table with what you think ci+1 and s should be. A few have already been filled in for you.
Input |
Output |
||||
x |
y |
ci |
ci+1 |
s |
|
0 |
0 |
0 |
0 |
0 |
|
0 |
0 |
1 |
0 |
1 |
|
0 |
1 |
0 |
0 |
1 |
|
0 |
1 |
1 |
1 |
0 |
|
1 |
0 |
0 |
0 |
1 |
|
1 |
0 |
1 |
1 |
0 |
|
1 |
1 |
0 |
1 |
0 |
|
1 |
1 |
1 |
1 |
1 |
You can use the Karnaugh Map reduction method to find the simplfied expressions and then draw the full adder circuit.
Here are the functions for your convenience.
s = x XOR y XOR ci ci+1 = xy + ci(x XOR y)